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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2022-04-05 20:02:51 +0300 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2022-04-06 12:54:43 +0300 |
| commit | 0be0b70df6611205ac392d0e21f7e077f3230ee6 (patch) | |
| tree | bef43915852beb1b8bb228f9873c4439bb638734 /tools/perf/scripts/python/intel-pt-events.py | |
| parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
pinctrl: alderlake: Fix register offsets for ADL-N variant
It appears that almost traditionally the N variants have deviations
in the register offsets in comparison to S one. This is the case
for Intel Alder Lake as well. Fix register offsets for ADL-N variant.
Fixes: 114b610b9048 ("pinctrl: alderlake: Add Intel Alder Lake-N pin controller support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/intel-pt-events.py')
0 files changed, 0 insertions, 0 deletions