riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT

Before cacheinfo can be built correctly, we need to initialize level
and type. Since RISC-V currently does not have a register group that
describes cache-related attributes like ARM64, we cannot obtain them
directly, so now we obtain cache leaves from the ACPI PPTT table
(acpi_get_cache_info()) and set the cache type through split_levels.

Suggested-by: Jeremy Linton <[email protected]>
Suggested-by: Sudeep Holla <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Sunil V L <[email protected]>
Reviewed-by: Jeremy Linton <[email protected]>
Reviewed-by: Sudeep Holla <[email protected]>
Signed-off-by: Yunhui Cui <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>

0 files changed, 0 insertions, 0 deletions