diff options
| author | Sakari Ailus <[email protected]> | 2020-07-07 10:08:01 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2020-12-07 15:49:01 +0100 |
| commit | fe52ece8d2e26bd4d38e2c99a7cd13d944c1ee98 (patch) | |
| tree | 2e53bbb49e28841693b20defa2bd79dc06cefed7 /tools/perf/scripts/python/futex-contention.py | |
| parent | cab27256e8b3a6529faab9fc00e40fcf60b16590 (diff) | |
media: ccs-pll: Fix condition for pre-PLL divider lower bound
The lower bound of the pre-PLL divider was calculated based on OP SYS
clock frequency which is also affected by the OP SYS clock divider. This
is wrong. The right clock frequency is that of the PLL output clock.
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions