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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-08-22 21:28:01 +0300 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2018-08-23 09:58:12 +0200 |
| commit | 9faf870e559a710c44e747ba20383ea82d8ac5d2 (patch) | |
| tree | 530c032c8d4ad6dcbe18f925d16bcc0260a36daf /tools/perf/scripts/python/futex-contention.py | |
| parent | 26caddf274cf1e89fd4ce44ab2b8dbc7a7f97681 (diff) | |
mmc: renesas_sdhi_internal_dmac: fix #define RST_RESERVED_BITS
The DM_CM_RST register actually has bits 0-31 defaulting to 1s and bits
32-63 defaulting to 0s -- fix off-by-one in #define RST_RESERVED_BITS.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions