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authorManasi Navare <[email protected]>2018-05-23 15:44:44 -0700
committerPaulo Zanoni <[email protected]>2018-06-01 16:14:38 -0700
commit51c83cfaf96382ab65717d694f80af86482ba795 (patch)
tree4eef84a067d74f440b9007052398f3758b56ff2c /tools/perf/scripts/python/futex-contention.py
parentf17ca5010c34e99e4035f22437f8b83452584a26 (diff)
drm/i915/icl: Get DDI clock for ICL based on PLLs.
PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. This gets a little tricky for ICL since there is no register bit that maps directly to the link clock. So this patch creates a separate function in intel_dpll_mgr.c to obtain the write array PLL Params and compares the set pll_params with the table to get the corresponding link clock. v2: - Fix the encoder type check (DK). - Improve our error checking, return a sane value (Mika, Paulo). - Fix table entries (Paulo). Cc: Rodrigo Vivi <[email protected]> Cc: Mika Kahola <[email protected]> Cc: Paulo Zanoni <[email protected]> Cc: Dhinakaran Pandiyan <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> [Paulo: implement v2] Signed-off-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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