diff options
| author | Andrew Lunn <[email protected]> | 2014-02-22 20:14:52 +0100 |
|---|---|---|
| committer | Jason Cooper <[email protected]> | 2014-02-22 20:43:49 +0000 |
| commit | 4b8f7a11c9fb680895e5079788653a59d6bdde16 (patch) | |
| tree | d20f78bd55eb043f8f9e1be5e702301263b73079 /tools/perf/scripts/python/futex-contention.py | |
| parent | 3c317d00ba4a9489c161857a574432c61fde4a2a (diff) | |
ARM: MM: Add DT binding for Feroceon L2 cache
Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.
Signed-off-by: Andrew Lunn <[email protected]>
Tested-by: Jason Gunthorpe <[email protected]>
Signed-off-by: Jason Cooper <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions