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| author | Chaotian Jing <chaotian.jing@mediatek.com> | 2017-10-16 09:46:36 +0800 |
|---|---|---|
| committer | Ulf Hansson <ulf.hansson@linaro.org> | 2017-11-02 15:20:25 +0100 |
| commit | 3c1a8844369880d077f858f448afc4ef553d962a (patch) | |
| tree | c6e483bbf89b0e45c3bc5693306eb9651c077796 /tools/perf/scripts/python/futex-contention.py | |
| parent | d9dcbfc880126b193eab418d7b64b3774cb57152 (diff) | |
mmc: mediatek: add support of source_cg clock
source clock need an independent cg to control, when doing clk mode
switch, need gate source clock to avoid hw issue(multi-bit sync hw hang)
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Tested-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/futex-contention.py')
0 files changed, 0 insertions, 0 deletions