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authorHaijun Liu <[email protected]>2022-05-06 11:12:59 -0700
committerDavid S. Miller <[email protected]>2022-05-09 10:51:58 +0100
commit39d439047f1dc88f98b755d6f3a53a4ef8f0de21 (patch)
tree71163f79e60fe933a1bbc24be14f836f22346b4f /tools/perf/scripts/python/futex-contention.py
parenta4ff365346c98081311c299955d91d657123e8aa (diff)
net: wwan: t7xx: Add control DMA interface
Cross Layer DMA (CLDMA) Hardware interface (HIF) enables the control path of Host-Modem data transfers. CLDMA HIF layer provides a common interface to the Port Layer. CLDMA manages 8 independent RX/TX physical channels with data flow control in HW queues. CLDMA uses ring buffers of General Packet Descriptors (GPD) for TX/RX. GPDs can represent multiple or single data buffers (DB). CLDMA HIF initializes GPD rings, registers ISR handlers for CLDMA interrupts, and initializes CLDMA HW registers. CLDMA TX flow: 1. Port Layer write 2. Get DB address 3. Configure GPD 4. Triggering processing via HW register write CLDMA RX flow: 1. CLDMA HW sends a RX "done" to host 2. Driver starts thread to safely read GPD 3. DB is sent to Port layer 4. Create a new buffer for GPD ring Note: This patch does not enable compilation since it has dependencies such as t7xx_pcie_mac_clear_int()/t7xx_pcie_mac_set_int() and struct t7xx_pci_dev which are added by the core patch. Signed-off-by: Haijun Liu <[email protected]> Signed-off-by: Chandrashekar Devegowda <[email protected]> Co-developed-by: Ricardo Martinez <[email protected]> Signed-off-by: Ricardo Martinez <[email protected]> Reviewed-by: Loic Poulain <[email protected]> Reviewed-by: Ilpo Järvinen <[email protected]> Reviewed-by: Sergey Ryazanov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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