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authorRamona Bolboaca <[email protected]>2022-08-31 16:30:21 +0300
committerJonathan Cameron <[email protected]>2022-09-05 18:08:34 +0100
commit0fea1007f0e68764aa18822bb6fa83d3809739e8 (patch)
treee5fdabff400ffdfe5fa84b52175e5dc638d9b73c /tools/perf/scripts/python/futex-contention.py
parent5a80c2572f5e40fc106fe9f372964935798dc637 (diff)
iio: adc: add max11205 adc driver
Adding support for max11205 16-bit single-channel ultra-low power delta-sigma adc. The MAX11205 is compatible with the 2-wire interface and uses SCLK and RDY/DOUT for serial communications. In this mode, all controls are implemented by timing the high or low phase of the SCLK. The 2-wire serial interface only allows for data to be read out through the RDY/DOUT output. Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX11205.pdf Signed-off-by: Ramona Bolboaca <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jonathan Cameron <[email protected]>
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