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authorDaniel Palmer <[email protected]>2022-10-22 15:34:04 +0200
committerStephen Boyd <[email protected]>2022-10-27 11:44:27 -0700
commitfadbafc1b7b7a36d479a8e34adc85e8f7c614a3e (patch)
tree5ec411b7bc2816f0cc73e8f3111ec389f4bd31c4 /tools/perf/scripts/python/flamegraph.py
parent9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff)
clk: mstar: msc313 cpupll clk driver
Add a driver for the CPU pll/ARM pll/MIPS pll that is present in MStar SoCs. Currently there is no documentation for this block so it's possible this driver isn't entirely correct. Only tested on the version of this IP in the MStar/SigmaStar ARMv7 SoCs. Signed-off-by: Daniel Palmer <[email protected]> Co-developed-by: Willy Tarreau <[email protected]> Signed-off-by: Willy Tarreau <[email protected]> Signed-off-by: Romain Perier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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