diff options
| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2023-05-29 11:37:47 +0530 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2023-06-05 14:19:32 +0300 |
| commit | cb2e701305f4ffe3a107c1d97f8588b4ed48ccb3 (patch) | |
| tree | cbd5a83125234df207b1874a0f465ed2c37cbceb /tools/perf/scripts/python/flamegraph.py | |
| parent | 40023959dbab3c6ad56fa7213770e63d197b69fb (diff) | |
drm/i915/display: Set correct voltage level for 480MHz CDCLK
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
v2: rebase
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230529060747.3972259-1-chaitanya.kumar.borah@intel.com
(cherry picked from commit 5a3c46b809d09f8ef59e2fbf2463b1c102aecbaa)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
0 files changed, 0 insertions, 0 deletions