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| author | Dilip Kota <eswara.kota@linux.intel.com> | 2020-07-17 14:27:54 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-07-22 01:55:57 +0100 |
| commit | 8743d2155aed9236202294e293ab13d33b3a7682 (patch) | |
| tree | 012e47018031f1412ca26d67126add81d684a0d6 /tools/perf/scripts/python/flamegraph.py | |
| parent | 94eca904cb97f9cfa90e3e558fb73c49d2e42f91 (diff) | |
spi: lantiq: Add fifo size bit mask in SoC specific data structure
On newer chipsets, SPI controller has fifos of larger size.
So add the fifo size bit mask entry in SoC specific data structure.
Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Link: https://lore.kernel.org/r/a0889abf17a9fbc7077f10be0f0342b7ebdf9361.1594957019.git.eswara.kota@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/flamegraph.py')
0 files changed, 0 insertions, 0 deletions