can: mcp251xfd: add support for internal PLL

The PLL is enabled if the configured clock is less than or equal to 10 times
the max clock frequency.

The device will operate with two different SPI speeds. A slow speed determined
by the clock without the PLL enabled, and a fast speed derived from the
frequency with the PLL enabled.

Link: https://lore.kernel.org/all/[email protected]
Link: https://lore.kernel.org/all/[email protected]
Co-developed-by: Magnus Aagaard Sørensen <[email protected]>
Signed-off-by: Magnus Aagaard Sørensen <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>

0 files changed, 0 insertions, 0 deletions