diff options
| author | Dinh Nguyen <[email protected]> | 2022-11-14 17:02:15 -0600 |
|---|---|---|
| committer | Ulf Hansson <[email protected]> | 2022-12-07 13:22:37 +0100 |
| commit | ef87bd81cb881377c1eaf512167b0522c825b012 (patch) | |
| tree | 47be039c443d7dbfb8363dfbc1efd3d8e56f3d19 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | ccfa2466a456f70c0bab0cd0b64d6c8996141d2e (diff) | |
mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase
The clock-phase settings for the SDMMC controller in the SoCFPGA
platforms reside in a register in the System Manager. Add a method
to access that register through the syscon interface.
Signed-off-by: Dinh Nguyen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ulf Hansson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions