diff options
| author | Wolfram Sang <[email protected]> | 2022-10-06 21:04:50 +0200 |
|---|---|---|
| committer | Ulf Hansson <[email protected]> | 2022-12-07 13:22:36 +0100 |
| commit | ec9e80ae1719de541c719116a1ca0a0c70e9240c (patch) | |
| tree | bbfdb6e1afde22fe228229e8400c1361944a396b /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | af728d7ae20483add9f8d3c81280dc6298a0aa2e (diff) | |
mmc: renesas_sdhi: add quirk for broken register layout
Some early Gen3 SoCs have the DTRANEND1 bit at a different location than
all later SoCs. Because we need the bit soon, add a quirk so we know
which bit to use.
Signed-off-by: Wolfram Sang <[email protected]>
Tested-by: Duy Nguyen <[email protected]>
Tested-by: Yoshihiro Shimoda <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Ulf Hansson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions