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| author | Chris Wilson <[email protected]> | 2011-04-04 09:44:39 +0100 |
|---|---|---|
| committer | Keith Packard <[email protected]> | 2011-06-09 21:51:16 -0700 |
| commit | e4ffd173a1c2f96b43127c2537dd99d89e759bba (patch) | |
| tree | 932a67f5eebb7884ba6b28a4ebf0893d84a44eec /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | d5bd144959e639443f387c34989cec7c9efff091 (diff) | |
drm/i915: Add an interface to dynamically change the cache level
[anholt v2: Don't forget that when going from cached to uncached, we
haven't been tracking the write domain from the CPU perspective, since
we haven't needed it for GPU coherency.]
[ickle v3: We also need to make sure we relinquish any fences on older
chipsets and clear the GTT for sane domain tracking.]
Signed-off-by: Chris Wilson <[email protected]>
Signed-off-by: Eric Anholt <[email protected]>
Reviewed-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions