diff options
| author | Dmitry Osipenko <[email protected]> | 2014-12-12 18:19:19 +0300 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2015-01-07 15:39:39 +0100 |
| commit | de47699d005996b41cea590c6098078ac12058be (patch) | |
| tree | 7e056cf0a62d5972404ae2ce6813a53fa4bb20f2 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 8325aa30f8ada22731276b19a72310150f30b3ec (diff) | |
ARM: dts: tegra20: fix GR3D, DSI unit and reg base addresses
Commit 58ecb23f64ee ("ARM: tegra: add missing unit addresses to DT") added
unit address and changed reg base for GR3D and DSI host1x modules, but these
addresses belongs to GR2D and TVO modules respectively. Fix it by changing
modules unit and reg base addresses to proper ones.
Signed-off-by: Dmitry Osipenko <[email protected]>
Fixes: 58ecb23f64ee (ARM: tegra: add missing unit addresses to DT)
Cc: <[email protected]> # v3.13+
Reviewed-by: Alexandre Courbot <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions