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authorSean Anderson <[email protected]>2022-03-03 17:35:43 -0500
committerThierry Reding <[email protected]>2022-04-22 18:30:44 +0200
commitbc1ce713a0843ba14a1e00d5275ad42a8873a5ce (patch)
treefc4c5200109eaddbba0267c60f5732677b936b03 /tools/perf/scripts/python/failed-syscalls-by-pid.py
parentf643490e1bf941600f6105e4d27c49054fb6d562 (diff)
pwm: Add support for Xilinx AXI Timer
This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly found on Xilinx FPGAs. At the moment clock control is very basic: we just enable the clock during probe and pin the frequency. In the future, someone could add support for disabling the clock when not in use. Some common code has been specially demarcated. While currently only used by the PWM driver, it is anticipated that it may be split off in the future to be used by the timer driver as well. This driver was written with reference to Xilinx DS764 for v1.03.a [1]. [1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf Signed-off-by: Sean Anderson <[email protected]> Acked-by: Michal Simek <[email protected]> Reviewed-by: Uwe Kleine-König <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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