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| author | Akshay Bhat <akshay.bhat@timesys.com> | 2016-04-18 17:19:44 -0400 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2016-04-26 11:05:30 +0800 |
| commit | b492b8744da9b205b9b303b111a138b16d56e712 (patch) | |
| tree | a5f5917a3a7303f3d56f5fe20f4cfd023d8e37cb /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 7532c98f3ac212ca1f19be7e628356247b616c74 (diff) | |
ARM: dts: imx6q-b850v3: Update display clock source
The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions