diff options
| author | William Qiu <[email protected]> | 2023-09-22 14:28:34 +0800 |
|---|---|---|
| committer | Conor Dooley <[email protected]> | 2023-09-30 09:58:30 +0100 |
| commit | af571133f7ae028ec9b5fdab78f483af13bf28d3 (patch) | |
| tree | cb477c7a1ce4e73986267c24fe35ed26e6709a8b /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | be326bee09374a2ebd18cb5af8fcd6f1e7825260 (diff) | |
riscv: dts: starfive: add assigned-clock* to limit frquency
In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.
Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions