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authorPing-Ke Shih <[email protected]>2022-05-16 08:52:15 +0800
committerKalle Valo <[email protected]>2022-05-17 18:32:00 +0300
commita456021c6f1482b94dce77ebaeef77412cd37dba (patch)
tree095783f675d34417330d123ceb5b67c546dd88a8 /tools/perf/scripts/python/failed-syscalls-by-pid.py
parenta06d2dd7e22f93f98beb15c5ae919f6a58fd2635 (diff)
rtw89: pci: only mask out INT indicator register for disable interrupt v1
The design of INT indicator register (R_AX_PCIE_HIMR00_V1) is to reduce IO during frequent interrupts, because it can stop chip sending interrupt to host if we just set this indicator to 0, not all IMR(s). This indicator register looks like a root interrupt controller of wifi chip. However, we can't set all other IMR(s) to 0 during we are running on interrupt service routine, or the indicator register can't reflect the status of certain interrupt happened during this period, and then miss some interrupts especially SER interrupt events. Signed-off-by: Ping-Ke Shih <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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