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authorVille Syrjälä <[email protected]>2015-03-02 20:07:17 +0200
committerDaniel Vetter <[email protected]>2015-03-17 22:30:10 +0100
commit9d0d3fdaae08e9221070dda32348116c2a3235ed (patch)
tree4786e314f39b7bdab21788094bb1dd2fb1f665f1 /tools/perf/scripts/python/failed-syscalls-by-pid.py
parent6cca31950a5df57d89d9cb4f846c96dab902adf9 (diff)
drm/i915: Fix chv cdclk support
The specs seem to be full of misinformation wrt. the Punit register 0x36. Some versions still show the old VLV bit layout, some the new layout, and all of them seem to tell us nonsense about the cdclk value encoding. Testing on actual hardware has shown that we simply need to program the desired CCK divider into the Punit register using the new layout of the bits. Doing that, the status bit change to indicate the same value, and the CCK 0x6b register also changes accordingly to indicate that CCK is now using the new divider. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Vijay Purushothaman <[email protected]> Reviewed-by: Yogesh Mohan Marimuthu <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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