aboutsummaryrefslogtreecommitdiff
path: root/tools/perf/scripts/python/failed-syscalls-by-pid.py
diff options
context:
space:
mode:
authorMarek Vasut <[email protected]>2017-07-09 15:28:13 +0200
committerStephen Boyd <[email protected]>2017-07-17 11:51:00 -0700
commit73100e79c7368dd30c06bcfc04252bab5dc48783 (patch)
tree478a2ca153a74a56fe1a794e5e19cb208910e4fa /tools/perf/scripts/python/failed-syscalls-by-pid.py
parent8c1ebe9762670159ca982167131af63c94ff1571 (diff)
clk: vc5: Add bindings for IDT VersaClock 5P49V6901
IDT VersaClock 6 5P49V6901 has 4 clock outputs, 4 fractional dividers. Input clock source can be taken from either external crystal or from external reference clock. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexey Firago <[email protected]> Cc: Rob Herring <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: [email protected] Cc: [email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions