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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-22 13:50:26 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:44:18 +0200 |
| commit | 724620bd711364f352d13563d48ade7b5c5ea297 (patch) | |
| tree | 4fe44add1af12e1e64c6b64fc25d9bc789db41a7 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 1b131e08e7f2b2271a32361bb0ae466d6cc50fbd (diff) | |
clk: renesas: rcar-gen4: Add support for variable fractional PLLs
The custom clock driver that models PLL clocks on R-Car Gen4 supports
PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same
control register layout.
Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new
clock type and helper macro to describe these PLLs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions