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| author | Elaine Zhang <[email protected]> | 2017-08-21 16:16:07 +0800 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2017-08-22 02:55:03 +0200 |
| commit | 64a1644bc3baa62b769455d811b7999b9a1c6cd1 (patch) | |
| tree | 45c504a9756f007b43db6793b1dd815608749418 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | c7d0045b08a36c2fb7874efc48d747613c6a1ccf (diff) | |
clk: rockchip: fix the rv1108 clk_mac sel register description
The source clock ordering is wrong, as shown in the TRM:
cru_sel24_con[8]
rmii_extclk_sel
clock source select control register
1'b0: from internal PLL
1'b1: from external IO
Signed-off-by: Elaine Zhang <[email protected]>
Reviewed-by: David Wu <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions