diff options
| author | Evgenii Stepanov <[email protected]> | 2021-05-20 18:00:23 -0700 |
|---|---|---|
| committer | Will Deacon <[email protected]> | 2021-05-25 19:21:58 +0100 |
| commit | 3d0cca0b02ac98eac9157b26cf3951997db68b37 (patch) | |
| tree | 63faa9f036f3d926c0dc915cae59ecda399852dc /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | c4681547bcce777daf576925a966ffa824edd09d (diff) | |
kasan: speed up mte_set_mem_tag_range
Use DC GVA / DC GZVA to speed up KASan memory tagging in HW tags mode.
The first cacheline is always tagged using STG/STZG even if the address is
cacheline-aligned, as benchmarks show it is faster than a conditional
branch.
Signed-off-by: Evgenii Stepanov <[email protected]>
Co-developed-by: Peter Collingbourne <[email protected]>
Signed-off-by: Peter Collingbourne <[email protected]>
Reviewed-by: Catalin Marinas <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions