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| author | Vladimir Barinov <[email protected]> | 2017-07-09 20:40:05 +0300 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2017-07-17 11:51:00 -0700 |
| commit | 3a11c6618e176aecf129c6d2f0cbc9440672f378 (patch) | |
| tree | 7714295489241cfd13ddb0ba856ab2be9e83c79f /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | b191155541f2a4cfbe62697c8d65919549f948c0 (diff) | |
dt: Add bindings for IDT VersaClock 5P49V5925
IDT VersaClock 5 5P49V5925 has 5 clock outputs, 4 fractional dividers.
Input clock source can be taken only from external reference clock.
Signed-off-by: Vladimir Barinov <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions