diff options
| author | Ludovic Desroches <[email protected]> | 2016-02-22 15:18:55 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2016-03-07 16:11:14 -0800 |
| commit | 2958ccee3690717f711431b546d7f194d8fa4f8b (patch) | |
| tree | 38686fd3ebb38d0e357b3722c97106397afb09d4 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | f4a8ab04ddde078a9e9906e1ca8d6821ac91e717 (diff) | |
tty/serial: at91: fix bad offset for UART timeout register
With SAMA5D2, the UART has hw timeout but the offset of the register to
define this value is not the same as the one for USART.
When using the new UART, the value of this register was 0 so we never
get timeout irqs. It involves that when using DMA, we were stuck until
the execution of the dma callback which happens when a buffer is full
(so after receiving 2048 bytes).
Signed-off-by: Ludovic Desroches <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions