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| author | Ping-Ke Shih <[email protected]> | 2022-03-25 14:00:43 +0800 |
|---|---|---|
| committer | Kalle Valo <[email protected]> | 2022-04-06 11:55:13 +0300 |
| commit | 0db862fb025c933675e3efb388eb96da781d6365 (patch) | |
| tree | 7d26dcd8550c7757308b7441d91bc087dd756e49 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 1e3f205548155af7df781bb23bed15af17aa8ace (diff) | |
rtw89: pci: add LTR setting for v1 chip
Add LTR handle to PCI deinit as well.
Signed-off-by: Ping-Ke Shih <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions