diff options
| author | Laxman Dewangan <[email protected]> | 2017-05-02 19:35:37 +0530 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2017-06-13 14:30:22 +0200 |
| commit | 0527eb372301bfd9b84160adb6c132b443ae3013 (patch) | |
| tree | d016dee26d584a2579fd2b20c916cf2a062d3cb5 /tools/perf/scripts/python/failed-syscalls-by-pid.py | |
| parent | 2ea659a9ef488125eb46da6eb571de5eae5c43f6 (diff) | |
pwm: tegra: Set maximum pwm clock source per SoC tapeout
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 48 MHz.
In Tegra186, it is 102 MHz.
Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.
Signed-off-by: Laxman Dewangan <[email protected]>
Acked-by: Jon Hunter <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/failed-syscalls-by-pid.py')
0 files changed, 0 insertions, 0 deletions