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authorTrigger Huang <[email protected]>2019-06-03 16:48:17 +0800
committerAlex Deucher <[email protected]>2019-06-11 12:39:51 -0500
commite0301317acfed896c3bcbcbdf33f67f55c9d602b (patch)
tree76764f8fd4eedc65469d6b681244ead788e2787c /tools/perf/scripts/python/exported-sql-viewer.py
parente038b9016aa88a9e1429f1b016644c509b8e58a6 (diff)
drm/amdgpu: Hardcode reg access using L1 security
Under Vega10 SR-IOV VF, L1 register access mode should be enabled by default as the non-security VF will no longer be supported. Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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