drm/i915/adl_s: Configure Port clock registers for ADL-S

Add changes to configure port clock registers for ADL-S. Combo phy port
clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers.

The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S
translates to
DDI A -> DDIA
DDI B -> USBC1
DDI I -> USBC2

For DPCLKA_CFGCR1
DDI J -> USBC3
DDI K -> USBC4

Bspec: 50287
Bspec: 53812
Bspec: 53723

v2: Replace I915_READ() with intel_de_read().(Jani)

v3:
- Use reg variable to assign ADLS specific registers inorder to replace
  branching with intel_de_read/write() calls.(mdroper)
- Reuse icl_get_ddi_pll() for ADLS to fix issue with updating active
  dpll on driver load.(aswarup)

Cc: Jani Nikula <[email protected]>
Cc: Ville Syrjälä <[email protected]>
Cc: Imre Deak <[email protected]>
Cc: Matt Roper <[email protected]>
Cc: Lucas De Marchi <[email protected]>
Signed-off-by: Aditya Swarup <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Signed-off-by: Lucas De Marchi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

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