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author | Qiang Yu <[email protected]> | 2024-10-11 03:41:39 -0700 |
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committer | Bjorn Andersson <[email protected]> | 2024-10-16 15:21:40 -0500 |
commit | bf0a800415a7397617765fe5f5278a645195c75a (patch) | |
tree | 1505bf4cc1f249debcec84396a2c1166468b4d7c /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | e02bfea4d7ef587bb285ad5825da4e1973ac8263 (diff) |
clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks
The pipediv2_clk's source from the same mux as pipe clock. So they have
same limitation, which is that the PHY sequence requires to enable these
local CBCs before the PHY is actually outputting a clock to them. This
means the clock won't actually turn on when we vote them. Hence, let's
skip the halt bit check of the pipediv2_clk, otherwise pipediv2_clk may
stuck at off state during bootup.
Cc: [email protected]
Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Suggested-by: Mike Tipton <[email protected]>
Signed-off-by: Qiang Yu <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Reviewed-by: Johan Hovold <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions