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| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-06-20 17:26:42 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2024-06-27 10:44:24 +0200 |
| commit | a5c05453a13ab324ad8719e8a23dfb6af01f3652 (patch) | |
| tree | d18ef9dcf6d3c8789003228ee29a9a8813b2bfd9 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 7c48090af524410fe72754be5f4cfd92d9487957 (diff) | |
mips: bmips: rework and cache CBR addr handling
Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.
This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.
bmips_cbr_addr is defined in setup.c for each arch to keep compatibility
with legacy brcm47xx/brcm63xx and generic BMIPS target.
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions