diff options
author | Ahmad Fatoum <[email protected]> | 2022-03-02 09:34:28 +0100 |
---|---|---|
committer | Mark Brown <[email protected]> | 2022-03-07 13:13:10 +0000 |
commit | a50b7926d015c3b8194ab1d7c8aa86db8e4b7700 (patch) | |
tree | fec04b90b5e2d2b4b0669e547839b773506e9de7 /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | 1d4cbdf7bf2eaa794528250a29aed08f1df7f837 (diff) |
ASoC: fsl_sai: implement 1:1 bclk:mclk ratio support
With higher channel counts, we may need higher clock rates. Starting
with SAI v3.1 (i.MX8MM), we can bypass the divider and get a 1:1
bclk:mclk ratio. Add the necessary support.
Signed-off-by: Viorel Suman <[email protected]>
Signed-off-by: Ahmad Fatoum <[email protected]>
Signed-off-by: Sascha Hauer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions