diff options
| author | Anson Huang <anson.huang@nxp.com> | 2019-04-30 00:57:22 +0000 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-05-01 14:01:45 -0700 |
| commit | a048fe996b5109d3c94c243bb0733419fbd0ed8f (patch) | |
| tree | e90c9313cf03c1683d6347e3a738abc583cc75d4 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 8cd117e712e17bc9af07638d73261603ef8f4e8d (diff) | |
clk: imx: pllv4: add fractional-N pll support
The pllv4 supports fractional-N function, the formula is:
PLL output freq = input * (mult + num/denom),
This patch adds fractional-N function support, including
clock round rate, calculate rate and set rate, with this
patch, the clock rate of APLL in clock tree is more accurate
than before:
Without fraction:
apll_pre_sel 1 1 1 24000000 0 0 50000
apll_pre_div 1 1 2 24000000 0 0 50000
apll 1 1 2 528000000 0 0 50000
apll_pfd3 0 0 0 792000000 0 0 50000
apll_pfd2 0 0 0 339428571 0 0 50000
apll_pfd1 0 0 0 352000000 0 0 50000
usdhc0 0 0 0 352000000 0 0 50000
apll_pfd0 1 1 1 352000000 0 0 50000
With fraction:
apll_pre_sel 1 1 1 24000000 0 0 50000
apll_pre_div 1 1 2 24000000 0 0 50000
apll 1 1 2 529200000 0 0 50000
apll_pfd3 0 0 0 793800000 0 0 50000
apll_pfd2 0 0 0 340200000 0 0 50000
apll_pfd1 0 0 0 352800000 0 0 50000
usdhc0 0 0 0 352800000 0 0 50000
apll_pfd0 1 1 1 352800000 0 0 50000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions