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| author | Lucas De Marchi <[email protected]> | 2019-07-08 10:28:14 -0700 |
|---|---|---|
| committer | Lucas De Marchi <[email protected]> | 2019-07-10 10:30:18 -0700 |
| commit | 9d44dcb9088aadd11718a7ad5a8567d6b8a1174a (patch) | |
| tree | 834843fd41fbc106cb14af49499e09c5fee7af1f /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | c99fd7b3908e287ccd20be4f9eefe597c7d354fd (diff) | |
drm/i915: move intel_ddi_set_fia_lane_count to intel_tc.c
PORT_TX_DFLEXDPMLE1 is a FIA register so move it to intel_tc.c where we
access other FIA registers. In Tiger Lake we have multiple/modular FIAs
so it makes sense to start moving all access to their registers to a
common place.
While at it, make it clear that we will only ever call this function
for ports with TC phy. Previously we were relying on tc_mode being
TC_PORT_TBT_ALT for combo phy ports. However it's confusing since in
this same function we have checks for is_tc_port. Also, if we manage to
make each phy access only their own field, we may in future add them as
a union inside intel_digital_port.
v2: Fix coding style while moving the code
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Imre Deak <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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