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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-03-12 10:01:34 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-04-02 11:05:30 +0200 |
| commit | 9c85158585214770a232ff2efdbdb0e75704743f (patch) | |
| tree | 7a564224c74e74305180b792b9f13753e04f54e6 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | e56321e48db4c57c9f389592ef6bbfb24affd0fd (diff) | |
clk: renesas: r8a779h0: Add SCIF clocks
Add the module clocks used by the Serial Communication Interfaces with
FIFO (SCIF) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/82d731edd4ae4a8cd7683368131095777f4fa172.1709741224.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions