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authorAndre Przywara <[email protected]>2020-04-30 22:10:47 +0100
committerRob Herring <[email protected]>2020-05-03 11:10:41 -0500
commit958ba5c2393732b1629afd00764020d17ea0ef26 (patch)
treeb7815b4fbc2b2a239f23fec11c741e7be238a686 /tools/perf/scripts/python/exported-sql-viewer.py
parent3d21a46093352f7802b9c66c7cce35cd02a50e53 (diff)
dt-bindings: clock: Convert Calxeda clock bindings to json-schema
Convert the Calxeda clock bindings to DT schema format using json-schema. This just covers the actual PLL and divider clock nodes. In the actual DTs they are somewhat unconnected (no ranges or bus compatible) children of the sregs node, but for the actual clock bindings this is not relevant. One oddity is that the addresses are relative to the parent node, without that being pronounced using a ranges property. But this is too late to fix now. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Rob Herring <[email protected]>
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