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| author | Anju T Sudhakar <[email protected]> | 2020-07-13 20:16:23 +0530 |
|---|---|---|
| committer | Michael Ellerman <[email protected]> | 2020-07-16 13:12:46 +1000 |
| commit | 77ca3951cc37727ae8361d583a30da7a1b84e427 (patch) | |
| tree | c4bac83d1ef6b6d7b20d2b2aebd0f2192a72ff7f /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 9a3e3dccbf4317d02d28f8f99a5d1ccce42f9922 (diff) | |
powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc
IMC trace-mode record has MSR[HV PR] bits added in the third DW.
These bits can be used to set the cpumode for the instruction pointer
captured in each sample.
Add support in kernel to use these bits to set the cpumode for
each sample.
Signed-off-by: Anju T Sudhakar <[email protected]>
Signed-off-by: Madhavan Srinivasan <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions