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authorJoseph Gravenor <[email protected]>2019-11-08 14:30:34 -0500
committerAlex Deucher <[email protected]>2019-12-05 16:28:50 -0500
commit639dcfc6feb5c7451d1382c5d3fa1fd679eca544 (patch)
tree62ee7f6e7239639be4ac0ae524e69778168f794b /tools/perf/scripts/python/exported-sql-viewer.py
parent8fb3a6363684b5f00e7b438e22fc17346711f4fa (diff)
drm/amd/display: have two different sr and pstate latency tables for renoir
[Why] new sr and pstate latencies are optimized for the case when we are not using lpddr4 memory [How] have two different wm tables, one for the lpddr case and one for non lpddr case Signed-off-by: Joseph Gravenor <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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