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| author | Jonathan Cameron <[email protected]> | 2022-05-08 18:56:19 +0100 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2022-06-14 11:53:15 +0100 |
| commit | 62fa19bf484bfeb52c56b7c6d6a6b1222c597f9c (patch) | |
| tree | 19276468d65657f8156ecad908e0d34743461454 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | a2105d87eb8eb03591515df10102e04a1c9e0e46 (diff) | |
iio: adc: ti-tlc4541: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to include 'may'.
Fixes: ac2bec9d587c ("iio: adc: tlc4541: add support for TI tlc4541 adc")
Signed-off-by: Jonathan Cameron <[email protected]>
Acked-by: Nuno Sá <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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