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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2024-03-21 16:46:24 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-04-21 12:31:41 -0500 |
| commit | 3b743d532eac3cd1ab8fb21e8bf0390715237d8b (patch) | |
| tree | 2b2fa66f04315e9c16e979735b0dd8e07adef7db /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 8e0a95add7e3f3838d5b494ce645c48759ba4168 (diff) | |
arm64: dts: qcom: sm8350: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
for each controller instance. Hence, add a node to represent the bridge.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-4-1eb790c53e43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions