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| author | Jonathan Cameron <[email protected]> | 2022-05-08 18:56:12 +0100 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2022-06-14 11:53:14 +0100 |
| commit | 23c81e7a7e5204a08b553d07362d3082926663b8 (patch) | |
| tree | 38f052b9982b12027160a13f2268ca5f07952f0a /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 76890c3bce6003caf53b283c49a210280cb8ea33 (diff) | |
iio: adc: ti-adc128s052: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 913b86468674 ("iio: adc: Add TI ADC128S052")
Signed-off-by: Jonathan Cameron <[email protected]>
Acked-by: Nuno Sá <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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