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| author | Hansen <Hansen.Dsouza@amd.com> | 2021-10-01 22:36:15 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-06 15:49:49 -0400 |
| commit | 07fe77c3ad96917a6d8386e3ae4f3cc37e60d505 (patch) | |
| tree | 66da190ad4a5f0bacbc162a75898c9760950537a /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | aa635f6509ce2e086da09d982abd32e3f652608c (diff) | |
drm/amd/display: Fix detection of 4 lane for DPALT
[Why]
DPALT detection for B0 PHY has its own set of RDPCSPIPE registers
[How]
Use RDPCSPIPE registers to detect if DPALT lane is 4 lane
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Solomon Chiu <solomon.chiu@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions