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authorMitul Golani <[email protected]>2024-06-10 12:51:54 +0530
committerSuraj Kandpal <[email protected]>2024-06-11 09:58:00 +0530
commitfc8fc81cb8302831146f806f96a50d6debf5aaf3 (patch)
treea8dbc370638d1267e26deaba9c6c1cdf7e1916bf /tools/perf/scripts/python/export-to-sqlite.py
parent76dbc41608167d531f9c45d60054fd1f76498785 (diff)
drm/i915: Update indentation for VRR registers and bits
Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. --v2: - Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit). - Fix all indentation related VRR registers and bits instead of checkpatch one. Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> Signed-off-by: Suraj Kandpal <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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