diff options
| author | Hans de Goede <[email protected]> | 2022-01-16 22:52:03 +0100 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2022-02-08 06:28:38 +0100 |
| commit | f88fba1a411cc461b2563fb08715831745012830 (patch) | |
| tree | ee53e46854f34f692b0472d86e1092fadcbabbed /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ee328dded2274a7e1a65988b289337d52e70951c (diff) | |
media: atomisp_gmin_platform: Base CsiPort default on detected CLK
On devices with 2 cameras and no _DSM / EFI-vars providing CsiPort
clock info, defaulting to CsiPort 0 obviously is wrong for 1 of the
2 cameras.
The Intel Cherry Trail (ISP2401) reference design combines:
pmc_plt_clk_2 with CsiPort 0
pmc_plt_clk_4 with CsiPort 1
The Intel Bay Trail (ISP2400) reference design combines:
pmc_plt_clk_1 with CsiPort 0
pmc_plt_clk_0 with CsiPort 1
Use this knowledge to set the default CsiPort value based on
the detected CLK for the sensor.
Link: https://lore.kernel.org/linux-media/[email protected]
Signed-off-by: Hans de Goede <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions