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| author | MD Danish Anwar <danishanwar@ti.com> | 2024-02-15 16:00:35 +0530 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2024-02-19 13:42:01 +0530 |
| commit | efb32a10a10d92f4bc3380106bd3b003ea790aa3 (patch) | |
| tree | 50d0b7ec2a6983337839361cf5a7c6c8863fb7b5 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | d4e8c8ad5d14ad51ed8813442d81c43019fd669d (diff) | |
arm64: dts: ti: k3-am642-evm: add ICSSG1 Ethernet support
ICSSG1 provides dual Gigabit Ethernet support with proper FW loaded.
The ICSSG1 MII0 (RGMII1) has DP83869 PHY attached to it. The ICSSG1 shares
MII1 (RGMII2) PHY DP83869 with CPSW3g and it's assigned by default to
CPSW3g. The MDIO access to MII1 (RGMII2) PHY DP83869 is controlled by MDIO
bus switch and also assigned to CPSW3g. Therefore the ICSSG1 MII1 (RGMII2)
port is kept disable and ICSSG1 is enabled in single MAC mode by
default.
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Link: https://lore.kernel.org/r/20240215103036.2825096-3-danishanwar@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions