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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-10-16 17:57:03 +0300 |
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committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2017-10-19 15:38:13 +0300 |
commit | edba48fdfc4770ee41d71e2c2c0360b15cca6567 (patch) | |
tree | 60dcce19fc83ec9f191019b71045cb0f433cd677 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 043eaf3685c8edccf5400a0260027b864b931797 (diff) |
drm/i915: Centralize the SKL DDI A/E vs. B/C/D buf trans handling
SKL DDI B/C/D only have 9 usable buf trans registers for DP/eDP. That
matches the normal DP buf trans tables, but the low vswing eDP tables
have 10 entries. Thus the eDP tables can only be used safely with DDI A
and E.
We try to catch cases where DDI B/C/D gets used with the wrong number of
entires in some parts of the code, but not everywhere. Let's move the
code to deal with that deeper into intel_ddi_get_buf_trans_edp(). And
for sake of symmetry do the same in intel_ddi_get_buf_trans_dp(). That
would also avoid explosions in the rather unlikely case that the DP
tables would get revised to 10 entries as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171016145705.11780-9-ville.syrjala@linux.intel.com
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions