diff options
| author | Wesley Chalmers <[email protected]> | 2022-11-03 22:29:31 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-04-18 16:28:51 -0400 |
| commit | e101bf95ea87ccc03ac2f48dfc0757c6364ff3c7 (patch) | |
| tree | 5212acf588ff539adc4704e6cc4e9279887e2fe8 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 6f0ef80a00adfd51be22b6ab84acd48de1d3938d (diff) | |
drm/amd/display: Do not set drr on pipe commit
[WHY]
Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a
pipe commit can cause underflow.
[HOW]
Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets
optimized_required.
This change expects that Freesync requests are blocked when
optimized_required is true.
Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Wesley Chalmers <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions